1. Technical Field
The present invention relates to a semiconductor device including a reference cell having a capacitance.
2. Related Art
When a read-out operation from a memory cell of a dynamic random access memory (DRAM) is conducted, the following processing is conducted. First of all, an electrical voltage of a bit line (data line) that is coupled to a target memory cell is set to a pre-charging voltage. Subsequently, a transistor of the memory cell is switched to “on”. At this time, a capacitance in the bit line set at the pre-charging voltage is coupled to a capacitance in its memory cell, an electric potential in the bit line is increased or decreased, depending on which value of 1 or 0 the memory cell stores. This variation is amplified with a sense amplifier in reference to the pre-charging electrical voltage to detect data stored in the memory cell.
Conventionally, a half voltage (½Vcc) of a charging voltage (Vcc) is employed for the pre-charging voltage. In addition, reduced charging voltage is employed for reducing a power consumption of DRAM in recent years. Therefore, if an electric potential difference between a drain and a source of a transistor in a memory cell is only ½Vcc, such smaller electric potential difference causes an increased time required for reading data out from the memory cell and detecting the data that have been stored in the memory cell with a sense amplifier.
In order to solve such problem, investigations in developments of a ground pre-charging DRAM, which utilize a pre-charging voltage of a bit line for a ground, are proceeded (Japanese Patent Laid-Open No. 2004-265,533). Such type of DRAM employs a reference cell (dummy cell) pre-charged with ½Vcc, and the memory cell is coupled to one of a pair of bit lines coupled to the sense amplifier and a reference cell is coupled to the other thereof. After pre-charging the pair of the bit lines at a level of the ground potential, capacitances of the memory cell and the reference cell are coupled to the bit lines, respectively. Then, a potential difference between an output from the memory cell and an output from the reference cell is detected and amplified with a sense amplifier to obtain data of the memory cell.
As such, the potential difference between the drain and the source of the transistor in the memory cell can be increased by utilizing the ground potential for the pre-charging voltage, and therefore it is expected that the time required for reading data out from the memory cell and detecting the data that have been stored in the memory cell with a sense amplifier is reduced.
Since the reference cells are required for the ground pre-charging DRAM, it is necessary to have ideas for suppressing an increase in area of a semiconductor device by highly effectively arranging the reference cells. Further, a path for coupling the reference cell to a constant-voltage source is required for setting the capacitance of the reference cell at a predetermined voltage.